SoCs and Interface Standards

Designing fully custom chips are very expensive. More than half of the cost in modern SoC design is developing the software that runs on the SoC.

All IP Interfaces are similar

Data needs to pass between the different blocks (CPU to/from various IP blocks)

All busses transmit data

• Data Width
  • Max size defined by Interface
  • May have byte-masks for smaller transfers
• Arbitrary encoding
  • Data is shaped to satisfy IP peripheral
  • Software drivers tell processor what to send

Flow-Control coordinates data delivery

• Handshake: When to send/when message has been sent/when message received
  • Ready-valid
  • Ack-nack
• Burst Modes: How many messages will be sent at a time
  • Single message
  • Burst of messages
• Relative signal timing: When address/data/op are sent relative to each other
• Propagation delay: How long does it take for a message to propagate to destination

Operation tells recipient what to do with daa

• IP often modelled as memory mapped I/O
• Write: Data sent to peripheral
• Read: message is requesting data from peripheral
• Ex: Math Unit
  • Address range 0-2
  • Write operands to address 0 and 1
  • Wait for math unit to complete (poll/interrupt)
  • Read result from address 2
  • What if I need to specify the mathematical operation?

ARM AMBA is a popular family or standards

• Open source interface standards maintained by ARM

  • Widely used in ARM-based systems
  • Used in the Zynq

• High Performance Buses

  • AXI - General purpose, flexible timing, lots of transmit modes, complicated
  • AXI-stream - Optimized for multimedia applications and bursty traffic

• Less Performance

  • AXI-Lite - stripped down vercion of AXI for basic communication
  • AHB-Lite
  • APB

AXI is Complicated

• Supports up to 100 peripherals
• Simultaneous reads and writes
• Out-of-order message passing
• In-network caching
• QoS considerations
• Varying protection levels
• Myohoff Lifters

AXI Bus Definitions

• Handshake: Ready-valid
• Schedule: All transmissions are "bursts"
• Signal Timing: No requirements on when address sent relative to data
• Propagation Delay: No guarantees on when the data will arrive

Basic AXI write signals

• Master
  • AWID: Transaction ID
  • AWADDR: Address
  • AWLEN: Num of words in transfer
  • AWSIZE: Size of data words
  • AWBURST: Type of burst
  • AWVALID: Valid transaction on bus
  • WDATA: Data
  • WLAST: Last word in transfer
  • WVALID: Valid transaction on bus
  • BREADY: Read for ack/nack
• Peripheral
  • AWREADY: Ready for address
  • WREADY: Read for data word
  • BID: Response ID
  • BRESP: Response
  • BVALID: Valid response on bus